DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Jung Hoon | ko |
dc.contributor.author | Kim, Han Joon | ko |
dc.contributor.author | Shin, Minjeong | ko |
dc.contributor.author | Kim, John Dongjun | ko |
dc.contributor.author | Huh, Jaehyuk | ko |
dc.date.accessioned | 2014-12-08T04:53:14Z | - |
dc.date.available | 2014-12-08T04:53:14Z | - |
dc.date.created | 2013-07-03 | - |
dc.date.created | 2013-07-03 | - |
dc.date.issued | 2014-09 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON COMPUTERS, v.63, no.9, pp.2316 - 2329 | - |
dc.identifier.issn | 0018-9340 | - |
dc.identifier.uri | http://hdl.handle.net/10203/191276 | - |
dc.description.abstract | Hardware prefetching has become an essential technique in high performance processors to hide long external memory latencies. In multi-core architectures with cores communicating through a shared on-chip network, traffic generated by the prefetchers can account for up to 60% of the total on-chip network traffic. However, the distinct characteristics of prefetch traffic have not been considered in on-chip network design. In addition, prefetchers have been oblivious to the network congestion. In this work, we investigate the interactions between prefetchers and on-chip networks, exploiting the synergy of these two components in multi-cores. Firstly, we explore the design space of prefetch-aware on-chip networks. Considering the difference between prefetch and non-prefetch packets, we propose a priority-based router design, which selects non-prefetch packets first over prefetch packets. Secondly, we investigate network-aware prefetcher designs. We propose a prefetch control mechanism sensitive to network congestion-throttling prefetch requests based on the current network congestion. Our evaluation with full system simulations shows that the combination of the proposed prefetch-aware router and congestion-sensitive prefetch control improves the performance of benchmark applications by 11-12% with out-of-order cores, and 21-22% with SMT cores on average, up to 37% on some of the workloads. | - |
dc.language | English | - |
dc.publisher | IEEE COMPUTER SOC | - |
dc.subject | INTERCONNECTION NETWORKS | - |
dc.subject | FLOW-CONTROL | - |
dc.subject | PERFORMANCE | - |
dc.subject | MULTIPROCESSORS | - |
dc.title | Mutually Aware Prefetcher and On-Chip Network Designs for Multi-Cores | - |
dc.type | Article | - |
dc.identifier.wosid | 000343886200016 | - |
dc.identifier.scopusid | 2-s2.0-84928137987 | - |
dc.type.rims | ART | - |
dc.citation.volume | 63 | - |
dc.citation.issue | 9 | - |
dc.citation.beginningpage | 2316 | - |
dc.citation.endingpage | 2329 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON COMPUTERS | - |
dc.identifier.doi | 10.1109/TC.2013.99 | - |
dc.contributor.localauthor | Kim, John Dongjun | - |
dc.contributor.localauthor | Huh, Jaehyuk | - |
dc.contributor.nonIdAuthor | Shin, Minjeong | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Computer architecture | - |
dc.subject.keywordAuthor | on-chip networks | - |
dc.subject.keywordAuthor | flow controls | - |
dc.subject.keywordAuthor | muti-cores | - |
dc.subject.keywordAuthor | hardware prfetcher | - |
dc.subject.keywordAuthor | memory hierarchies | - |
dc.subject.keywordPlus | INTERCONNECTION NETWORKS | - |
dc.subject.keywordPlus | FLOW-CONTROL | - |
dc.subject.keywordPlus | PERFORMANCE | - |
dc.subject.keywordPlus | MULTIPROCESSORS | - |
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