DRAM power-aware rank scheduling디램 파워를 고려한 랭크 스케쥴링

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Modern DRAMs provide multiple low-power states to save their energy consumption during idle times. The use of low-power states, however, can cause performance degradation because state transitions from a low-power state to an active state incur time penalty. In this paper, we propose DRAM power-aware rank scheduling to save DRAM energy consumption. Our DRAM power-aware rank scheduling scheme is applied to the last-level cache and the memory controller. Our scheme utilizing the last-level cache reduces the number of write requests to DRAM and the number of state transitions by selecting victim cache block with considering cache block state and ranks state. In addition, our scheme utilizing the memory controller reinforces the effect of our scheme utilizing the last-level cache. Our scheme utilizing the memory controller increases DRAM rank idleness and decreases the number of state transitions by rank state-aware batch write. To verify the effectiveness of our proposed scheme, we compared our scheme with the conventional scheme which uses multiple low-power states. With our scheme, write requests are reduced by 10.8\% on average. Performance is improved by 0.3\% and DRAM power and energy consumption is reduced by 11.2\% and 11.4\%, respectively, on average.
Advisors
Kim, Soon Taeresearcher김순태
Description
한국과학기술원 : 전산학과,
Publisher
한국과학기술원
Issue Date
2012
Identifier
487452/325007  / 020103112
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전산학과, 2012.2, [ vii, 42 p. ]

Keywords

디램; 파워; 랭크; 스케쥴링; DRAM; POWER; RANK; SCHEDULING; REPLACEMENT; 교환정책

URI
http://hdl.handle.net/10203/180524
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=487452&flag=dissertation
Appears in Collection
CS-Theses_Master(석사논문)
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