Exploiting New Interconnect Technologies in On-Chip Communication

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The continuing scaling of transistors has increased the number of cores available in current processors, and the number of cores is expected to continue to increase. In such manycore processors, the communication between cores with the on-chip interconnect is becoming a challenge as it not only must provide low latency and high bandwidth but also needs to be cost-effective in terms of power consumption. The communication challenge is not only within a single chip but providing high bandwidth to the increasing number of cores from off-chip memory is also a challenge. The conventionalmetal interconnect is limited, especially for global communication, and can not scale efficiently. In this paper, we investigate alternative interconnect technologies that can be exploited to address the communication challenges in future manycore processor. We provide an overview of the different technologies that are available and then, investigate how these interconnect technologies impact the architecture of the on-chip communication and the system design.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2012
Language
English
Article Type
Article
Citation

IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS, v.2, no.2, pp.124 - 136

ISSN
2156-3357
DOI
10.1109/JETCAS.2012.2201031
URI
http://hdl.handle.net/10203/174495
Appears in Collection
EE-Journal Papers(저널논문)
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