One division per clock pipelined division architecture based on LAPR(Lookahead of Partial-Remainder) for low-power ECC applications

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Issue Date
1997-08-18
Language
ENG
Citation

Proceedings of the 1997 International Symposium on Low Power Electronics and Design, pp.220 - 224

URI
http://hdl.handle.net/10203/116249
Appears in Collection
EE-Conference Papers(학술회의논문)
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