Physical-gap-channel graphene field effect transistor with high on/off current ratio for digital logic applications

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We propose and analyze an approach to secure a high on/off current ratio in a graphene field effect transistor (FET) by introducing a physical gap along the channel rather than by attempting to open the energy bandgap of graphene. The device simulation results of the newly proposed device structure reveal highly suppressed off-state current of similar to 10(-9) A/mu m, an on/off current ratio of more than seven orders of magnitude, and a subthreshold slope of 2.23 mV/decade more than a 20-fold reduction relative to the theoretical limitation of conventional metal-oxide-semiconductor FETs. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4756795]
Publisher
AMER INST PHYSICS
Issue Date
2012-10
Language
English
Article Type
Article
Keywords

I-MOS; DEVICE; CIRCUIT; STRAIN

Citation

APPLIED PHYSICS LETTERS, v.101, no.14

ISSN
0003-6951
DOI
10.1063/1.4756795
URI
http://hdl.handle.net/10203/102613
Appears in Collection
EE-Journal Papers(저널논문)
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