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| VLM-S용 선형열선절단기의 회전각 계산 이상호; 안동규; 양동열, 한국정밀공학회지, v.19, no.2, pp.87 - 94, 2002-02 |
| VLRU: Buffer management in client-server systems Lee, SJ; Chung, Chin-Wan, IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, v.E83D, no.6, pp.1245 - 1254, 2000-06 |
| VLSH: voronoi-based locality sensitive hashing = VLSH: 보로노이 기반 국지성 민감 해싱link Tieu Lin L Loi; Loi; et al, 한국과학기술원, 2013 |
| VLSH: Voronoi-based Locality Sensitive Hashing Loi, Tieu Lin; Heo, Jae-Pil; Lee, Junghwan; Yoon, Sung-Eui, 2013 IEEE/RSJ International Conference on Intelligent Robots and System, pp.5345 - 5352, IEEE, 2013-11-06 |
| VLSI architecture for deep convolutional neural networks = 심층 컨볼루셔널 신경망을 위한 VLSI 구조link Jo, Jihyuck; Park, In-Cheol; et al, 한국과학기술원, 2018 |
| VLSI Architecture for simultaneous capture and playback of 4K UHD Audio and video data from multiple channels Jang, Sung-Joon; Lee, Sang-Seol; Kim, Je Woo, 2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016, Institute of Electrical and Electronics Engineers Inc., 2017-10 |
| VLSI architecture for turbo and LDPC convolutional codes = 터보 및 LDPC 컨볼루션 코드를 위한 VLSI 구조link Yoo, Injae; 유인재; et al, 한국과학기술원, 2017 |
| VLSI architecture for wavelet vector quantization in wireless image communication = 무선 영상 통신을 위한 웨이블릿 벡터 양자화의 VLSI 구조 연구link Paek, Seung-Kwon; 백승권; et al, 한국과학기술원, 1999 |
| VLSI architecture of List Sphere Decoder Kim H.-S.; Seo S.-H.; Park, Sin Chong, 9th International Conference on Advanced Communication Technology, ICACT 2007, v.3, pp.1693 - 1696, 2007-02-12 |
| VLSI architectures for the wavelet-based video coding system = 웨이블릿 기반 비디오 코딩 시스템을 위한 VLSI 구조link Baek, Yun-Ju; 백윤주; et al, 한국과학기술원, 1997 |
| VLSI Chips for Intelligent Speech Acquisition and Information Extraction based on Human Auditory Models Lee, Soo-Young, International Conference on Information Acquisition, pp.0 - 0, 2004-06 |
| VLSI design using redundant binary number system : arithmetic components for floating-point datapath unit = 잉여 이진수 시스템을 이용한 VLSI 시스템 설계 : 부동소수점 연산기로의 적용link Han, Kyung-Nam; 한경남; et al, 한국과학기술원, 2002 |
| VLSI Implementaion of Radial Basis Fuction Network with Learning Capability Choi, Y.K.; Cho, J.; Lee, Soo-Young, International Conference on Neural Information Processing, pp.1341 - 1346, 1995-10 |
| VLSI implementation for high-throughput turbo decoder with parallel architecture = 병렬 구조를 가지는 고속 터보 디코드의 VLSI 구현link Kwak, Jae-Young; 곽재영; et al, 한국과학기술원, 2003 |
| VLSI Implementation for Interpolation-based Matrix Inversion for 802.11n Receivers Park, Sin Chong, ITC-CSCC2007 |
| VLSI Implementation for Interpolation-based Matrix Inversion for MIMO-OFDM Receivers Park, Sin Chong, WSEAS |
| VLSI implementation of area-efficient list sphere decoder Lee S.; Lee J.; Park, Sin Chong, 2006 International Conference on Communication Technology, ICCT '06, 2006-11-27 |
| VLSI Implementation of Area-efficient List Sphere Decoder Park, Sin Chong, ISPACS 2006 |
| VLSI implementation of ATM layer functions for ATM UNI/NNI Choi, SH; Kim, YS; Han, YM; Park, Hong-Shik, ITC-CSCC, v.49, no.6, pp.269 - 273, 대한전자공학회, 1996 |
| VLSI implementation of decoder for decompressing fractal-based compressed image Kim, KH; Hong, CY; Kim, Lee-Sup, Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS. Part 5 (of 6), pp.221 - 224, IEEE, 1998-05-31 |
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