VLSI architecture for wavelet vector quantization in wireless image communication

Abstract

In this thesis, a wavelet vector quantization algorithm and its VLSI architectures are proposed, which satisfy several design requirements for wireless image communication. Firstly, a real-time zerotree wavelet vector quantization (WVQ) is proposed for wavelet image compression. Conventional wavelet image compression algorithm cannot provide the real-time computation because they use iterative methods to decide zerotrees. In contrast, the proposed zerotree WVQ algorithm predicts in real-time zero-vector trees of insignificant wavelet vectors by a non-iterative decision rule and then encodes significant wavelet vectors by the classified VQ. These cause the zerotree WVQ algorithm to provide the best compromise between the coding performance and the computation time. Secondly, the semi-recursive DWT VLSI architecture is proposed, which has minimum H/W cost of internal word length, data-bus utilization and the number of functional units and registers. Furthermore, the semi-recursive DWT VLSI architecture exploits the overlapped block processing and hence has the minimum transposition storage size and the short latency. Finally, the cost-effective WVQ VLSI architecture is proposed, which has only one VQ module to execute in real-time the 3-stage MSVQ and the CVQ of the zerotree WVQ algorithm by utilizing the vacant cycles for zero-vector trees which are not transmitted. The VQ module exploits modified WTA and thus has minimum hardware cost for the real-time minimum distance calculation.