DC Field | Value | Language |
---|---|---|
dc.contributor.author | Shin, In-Sup | ko |
dc.contributor.author | Paik, Seung-Whun | ko |
dc.contributor.author | Shin, Dong-Wan | ko |
dc.contributor.author | Shin, Young-Soo | ko |
dc.date.accessioned | 2013-03-11T12:37:16Z | - |
dc.date.available | 2013-03-11T12:37:16Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2012-04 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.20, no.4, pp.593 - 604 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | http://hdl.handle.net/10203/99333 | - |
dc.description.abstract | Dual supply voltage design is widely accepted as an effective way to reduce the power consumption of CMOS circuits. In this paper, we propose a comprehensive design framework that includes dual-scheduling, dual-allocation, controller synthesis as well as layout generation. In particular, we address a problem of high-level synthesis with objective of minimizing power consumption of storage units and multiplexers using dual-V-dd; this is made possible by utilizing timing slack that is left in the data-path after operation scheduling. We use integer linear programming (ILP) and also provide heuristic algorithms to solve the dual-register and connection allocation. The physical layout of dual-circuits has to separate power rails of V-ddh and V-ddl cells from each other. We propose a voltage island based placement algorithm to relieve this restriction and allow more flexibility of placement. In experiments on benchmark designs implemented in 1.08 V (with V-ddl of 0.8 V) 65-nm CMOS technology, both switching and leakage power are reduced by 20% on average, respectively, compared to data-path with dual-V-dd applied to functional units alone. Detailed analysis of area and wirelength is performed to assess feasibility of the proposed method. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | LOW-POWER | - |
dc.subject | MULTIPLE VOLTAGES | - |
dc.subject | REGISTER ALLOCATION | - |
dc.subject | SUPPLY VOLTAGES | - |
dc.subject | ASSIGNMENT | - |
dc.subject | BINDING | - |
dc.title | HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures | - |
dc.type | Article | - |
dc.identifier.wosid | 000302085300002 | - |
dc.identifier.scopusid | 2-s2.0-84859008197 | - |
dc.type.rims | ART | - |
dc.citation.volume | 20 | - |
dc.citation.issue | 4 | - |
dc.citation.beginningpage | 593 | - |
dc.citation.endingpage | 604 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.identifier.doi | 10.1109/TVLSI.2011.2122310 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Shin, Young-Soo | - |
dc.contributor.nonIdAuthor | Shin, Dong-Wan | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | Dual supply voltages | - |
dc.subject.keywordAuthor | high-level synthesis (HLS) | - |
dc.subject.keywordAuthor | low power | - |
dc.subject.keywordAuthor | register allocation | - |
dc.subject.keywordPlus | LOW-POWER | - |
dc.subject.keywordPlus | MULTIPLE VOLTAGES | - |
dc.subject.keywordPlus | REGISTER ALLOCATION | - |
dc.subject.keywordPlus | SUPPLY VOLTAGES | - |
dc.subject.keywordPlus | ASSIGNMENT | - |
dc.subject.keywordPlus | BINDING | - |
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