DC Field | Value | Language |
---|---|---|
dc.contributor.author | Choi, Sung-Jin | ko |
dc.contributor.author | Han, Jin-Woo | ko |
dc.contributor.author | Moon, Dong-Il | ko |
dc.contributor.author | Choi, Yang-Kyu | ko |
dc.date.accessioned | 2013-03-09T02:36:18Z | - |
dc.date.available | 2013-03-09T02:36:18Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2010-05 | - |
dc.identifier.citation | IEEE ELECTRON DEVICE LETTERS, v.31, no.5, pp.393 - 395 | - |
dc.identifier.issn | 0741-3106 | - |
dc.identifier.uri | http://hdl.handle.net/10203/95142 | - |
dc.description.abstract | ABJT-based 1T-DRAM that utilizes a latch process is analyzed in an experimental assessment. The experimental study reveals that undesired activation of a parasitic BJT by a high leakage current inhibits aggressive scaling of a BJT-based 1T-DRAM. Given the importance of choosing proper operation biases, the drain voltage that triggers the latch process in the BJT-based 1T-DRAM should be reduced to avoid unwanted parasitic BJT activation. Hence, a heterogeneous source and drain is proposed to ensure the energy bandgap offset to silicon channel. A numerical evaluation confirms that a heterogeneous source and drain embedded structure is a promising candidate for high-density and low-power DRAM technologies. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | MOSFETS | - |
dc.title | Analysis and Evaluation of a BJT-Based 1T-DRAM | - |
dc.type | Article | - |
dc.identifier.wosid | 000277047300004 | - |
dc.identifier.scopusid | 2-s2.0-77951880271 | - |
dc.type.rims | ART | - |
dc.citation.volume | 31 | - |
dc.citation.issue | 5 | - |
dc.citation.beginningpage | 393 | - |
dc.citation.endingpage | 395 | - |
dc.citation.publicationname | IEEE ELECTRON DEVICE LETTERS | - |
dc.identifier.doi | 10.1109/LED.2010.2042675 | - |
dc.contributor.localauthor | Choi, Yang-Kyu | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | BJT | - |
dc.subject.keywordAuthor | BV(CEO) | - |
dc.subject.keywordAuthor | capacitorless DRAM | - |
dc.subject.keywordAuthor | heterogeneous | - |
dc.subject.keywordAuthor | heterojunction bipolar transistor (HBT) | - |
dc.subject.keywordAuthor | latch | - |
dc.subject.keywordAuthor | parasitic | - |
dc.subject.keywordAuthor | silicon carbide (SiC) | - |
dc.subject.keywordAuthor | valence band offset | - |
dc.subject.keywordAuthor | 1T-DRAM | - |
dc.subject.keywordPlus | MOSFETS | - |
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