Minimizing Leakage Power of Sequential Circuits through Mixed-V-t Flip-Flops and Multi-V-t Combinational Gates

Abstract

The current use of multi-V-t to control leakage power targets combinational gates, even though sequential elements such as flip-flops and latches also contribute appreciable leakage. We can, nevertheless, apply multi-V-t to flip-flops, but few can take advantage of high-V-t, which causes abrupt changes in timing. We combine low-and high-V-t at the transistor level to design mixed-V-t flip-flops with reduced leakage, an unchanged footprint, and a small increase in either setup time or clock-to-Q delay, but not both. An allocation algorithm for two V(t)s determines the V-t (mixed, high, or low) of each flip-flop and the V-t of each combinational gate (high or low) in a sequential circuit. Experiments with 65-nm technology show an average leakage saving of 42% compared to conventional multi-V-t approaches; the leakage of flip-flops alone is cut by 78%. This saving is largely unaffected by die-to-die or within-die process variations, which we show through simulations. Standard deviation of leakage caused by process variation is also reduced due to less use of low-V-t devices. We also extend our approach to three V(t)s, and obtain a further 14% reduction in leakage.