A 1.8-GHz CMOS Power Amplifier Using Stacked nMOS and pMOS Structures for High-Voltage Operation

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A class-E power amplifier is proposed in this study. It uses both nMOS and pMOS as switching devices to reduce the voltage stress of each transistor. A voltage-combining scheme with nMOS and pMOS is proposed, and a transformer is designed using this scheme. The power amplifier is implemented in a 0.18-mu m RF CMOS process. Measurements show a maximum output power of 30.2 dBm with 36.8% power-added efficiency at a 3.3-V supply voltage. The power amplifier sustains a supply voltage of up to 3.9 V.
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Issue Date
2009-11
Language
English
Article Type
Article
Keywords

DISTRIBUTED ACTIVE-TRANSFORMER; LINE TRANSFORMER; 0.18-MU-M CMOS; EFFICIENCY; ARCHITECTURE; COMBINER

Citation

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, v.57, no.11, pp.2652 - 2660

ISSN
0018-9480
DOI
10.1109/TMTT.2009.2031936
URI
http://hdl.handle.net/10203/93339
Appears in Collection
EE-Journal Papers(저널논문)
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