DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, KW | ko |
dc.contributor.author | Jung, SO | ko |
dc.contributor.author | Kim, Taewhan | ko |
dc.contributor.author | Kang, SM | ko |
dc.date.accessioned | 2013-03-04T00:01:00Z | - |
dc.date.available | 2013-03-04T00:01:00Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2003-04 | - |
dc.identifier.citation | ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, v.8, pp.203 - 213 | - |
dc.identifier.issn | 1084-4309 | - |
dc.identifier.uri | http://hdl.handle.net/10203/80983 | - |
dc.description.abstract | Minimum delay associated with the hold time requirement is of concern to circuit designers, since race-through hazards are inherent in any multiple clock organization or clock distribution tree irrespective of clock frequency. The monotonic property of domino logic aggravates the min-delay path failure through coupling-induced speedup. To tackle the min-delay problem for domino logic, we propose a min-delay optimization algorithm considering coupling effects. Experimental results indicate that our algorithm yields a significant increase of min-delay without incurring max-delay violation. | - |
dc.language | English | - |
dc.publisher | ASSOC COMPUTING MACHINERY | - |
dc.subject | TIMING ANALYSIS | - |
dc.title | Minimum delay optimization for domino logic circuits - A coupling-aware approach | - |
dc.type | Article | - |
dc.identifier.wosid | 000182126100003 | - |
dc.type.rims | ART | - |
dc.citation.volume | 8 | - |
dc.citation.beginningpage | 203 | - |
dc.citation.endingpage | 213 | - |
dc.citation.publicationname | ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS | - |
dc.identifier.doi | 10.1145/762488.762491 | - |
dc.contributor.localauthor | Kim, Taewhan | - |
dc.contributor.nonIdAuthor | Kim, KW | - |
dc.contributor.nonIdAuthor | Jung, SO | - |
dc.contributor.nonIdAuthor | Kang, SM | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | algorithms | - |
dc.subject.keywordAuthor | performance | - |
dc.subject.keywordAuthor | logic synthesis | - |
dc.subject.keywordAuthor | coupling | - |
dc.subject.keywordAuthor | domino logic | - |
dc.subject.keywordAuthor | delay minimization | - |
dc.subject.keywordPlus | TIMING ANALYSIS | - |
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