DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, CH | ko |
dc.contributor.author | Kim, O | ko |
dc.contributor.author | Kim, Beom-Sup | ko |
dc.date.accessioned | 2013-03-03T09:57:24Z | - |
dc.date.available | 2013-03-03T09:57:24Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2001-05 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.36, no.5, pp.777 - 783 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/78285 | - |
dc.description.abstract | This paper describes a 1.8-GHz self-calibrated phase-locked loop (PLL) implemented in 0.35-mum CMOS technology, The PLL operates as an edge-combining type fractional-N frequency synthesizer using multiphase clock signals from a ring-type voltage-controlled oscillator (VCO), A self-calibration circuit in the PLL continuously adjusts delay mismatches among delay cells in the ring oscillator, eliminating the fractional spur commonly found in an edge-combing fractional divider due to the delay mismatches. With the calibration loop, the fractional spurs caused hy the delay mismatches are reduced to -55 dBc, and the corresponding maximum phase offsets between the multiphase signals is less than 0.2 degrees, The frequency synthesizer PLL operates from 1.7 to 1.9 GHz and the closed-loop phase noise is -105 dBc/Hz at 100-kHz offset from the carrier. The overall circuit consumes 20 mA from a 3.0-V power supply. | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | RECEIVERS | - |
dc.title | A 1.8-GHz self-calibrated phase-locked loop with precise I/Q matching | - |
dc.type | Article | - |
dc.identifier.wosid | 000168315600009 | - |
dc.identifier.scopusid | 2-s2.0-0035335391 | - |
dc.type.rims | ART | - |
dc.citation.volume | 36 | - |
dc.citation.issue | 5 | - |
dc.citation.beginningpage | 777 | - |
dc.citation.endingpage | 783 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.contributor.localauthor | Kim, Beom-Sup | - |
dc.contributor.nonIdAuthor | Park, CH | - |
dc.contributor.nonIdAuthor | Kim, O | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | delay mismatch | - |
dc.subject.keywordAuthor | fractional-N frequency synthesizer | - |
dc.subject.keywordAuthor | I/Q signal generation | - |
dc.subject.keywordAuthor | PLL | - |
dc.subject.keywordAuthor | ring oscillator | - |
dc.subject.keywordAuthor | self-calibration | - |
dc.subject.keywordPlus | RECEIVERS | - |
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