Modeling of Edge Threshold Voltage of Mesa-lsolated n-Channel MOSFETs on Fully-Depleted Thin Film SOI
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | jae-woo park | ko |
| dc.contributor.author | chul-hi han | ko |
| dc.contributor.author | choong-ki kim | ko |
| dc.date.accessioned | 2013-02-25T12:54:06Z | - |
| dc.date.available | 2013-02-25T12:54:06Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 1994-07 | - |
| dc.identifier.citation | SOLID-STATE ELECTRONICS, v.37, no.7, pp.1449 - 1452 | - |
| dc.identifier.issn | 0038-1101 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/62327 | - |
| dc.language | English | - |
| dc.publisher | Pergamon-Elsevier Science Ltd | - |
| dc.subject | TRANSISTORS | - |
| dc.title | Modeling of Edge Threshold Voltage of Mesa-lsolated n-Channel MOSFETs on Fully-Depleted Thin Film SOI | - |
| dc.type | Article | - |
| dc.identifier.wosid | A1994NH00700018 | - |
| dc.type.rims | ART | - |
| dc.citation.volume | 37 | - |
| dc.citation.issue | 7 | - |
| dc.citation.beginningpage | 1449 | - |
| dc.citation.endingpage | 1452 | - |
| dc.citation.publicationname | SOLID-STATE ELECTRONICS | - |
| dc.contributor.localauthor | chul-hi han | - |
| dc.contributor.nonIdAuthor | jae-woo park | - |
| dc.contributor.nonIdAuthor | choong-ki kim | - |
| dc.type.journalArticle | Note | - |
| dc.subject.keywordPlus | TRANSISTORS | - |
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