Microwave frequency interconnection line model of a wafer level package

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dc.contributor.authorLee, Jko
dc.contributor.authorRyu, Wko
dc.contributor.authorKim, Jounghoko
dc.contributor.authorKim, Nko
dc.contributor.authorPak, Jko
dc.contributor.authorKim, JMko
dc.date.accessioned2007-06-20T05:04:37Z-
dc.date.available2007-06-20T05:04:37Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2002-08-
dc.identifier.citationIEEE TRANSACTIONS ON ADVANCED PACKAGING, v.25, pp.356 - 364-
dc.identifier.issn1521-3323-
dc.identifier.urihttp://hdl.handle.net/10203/553-
dc.description.abstractIn this paper, we introduce the microwave transmission characteristics of interconnection lines on a wafer level package (WLP) and also propose a precise microwave-frequency model of the WLP interconnections. The slow wave factor (SWF) and attenuation constant are measured and discussed. High-frequency measurement is described, based on two-port S-parameter measurements, using an on-wafer microwave probe with a frequency range of up to 5 GHz. The extracted model is represented in the form of distributed lumped circuit model elements and can be easily merged into SPICE simulations. From the extracted model, it was found that line capacitance and inductance per unit length are 0.110 pF/mm and 0.286 nH/mm, respectively. We have successfully applied the extracted model to the design and analysis of a Rambus memory module for time domain simulation and signal integrity simulation. From the simulation, it was found that the WLP has better high-frequency performance, because of its low package inductance, compared with the muBGA package, but longer propagation delay, because of the relatively high package capacitance.-
dc.description.sponsorshipThe authors wish to thank Y. T. Kwon and J. K. Hong, Package/Module Team, Hynix Semiconductor (formerly Hyundai Electronic Corporation, Ltd.), for their support.word,en
dc.languageEnglish-
dc.language.isoen_USen
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleMicrowave frequency interconnection line model of a wafer level package-
dc.typeArticle-
dc.identifier.wosid000180497000006-
dc.identifier.scopusid2-s2.0-0036706304-
dc.type.rimsART-
dc.citation.volume25-
dc.citation.beginningpage356-
dc.citation.endingpage364-
dc.citation.publicationnameIEEE TRANSACTIONS ON ADVANCED PACKAGING-
dc.embargo.liftdate9999-12-31-
dc.embargo.terms9999-12-31-
dc.contributor.localauthorKim, Joungho-
dc.contributor.nonIdAuthorLee, J-
dc.contributor.nonIdAuthorRyu, W-
dc.contributor.nonIdAuthorKim, N-
dc.contributor.nonIdAuthorPak, J-
dc.contributor.nonIdAuthorKim, JM-
dc.type.journalArticleArticle; Proceedings Paper-
dc.subject.keywordAuthorlumped circuit model-
dc.subject.keywordAuthorRambus DRAM-
dc.subject.keywordAuthorS-parameter measurement-
dc.subject.keywordAuthorwafer level package-
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