Implementation of efficient FFT processor for 802.11a system

Abstract

High performance fast Fourier Transform (FFT) processors are widely used in different areas of application such as communications, radars, imaging, etc. This paper describes the efficient memory-based FFT processor, which can be implemented in 802.11a system. Through analyzing the organization of the memory-based FFT processor, I propose a new addressing scheme, which not only allows access to all the data needed for the butterfly computation simultaneously, but also reduces hardware complexity. Much power consumption in memory and complex multiplier is saved by using butterfly sequence ordering.