Browse "EE-Conference Papers(학술회의논문)" by Author Loh, WY
Showing results 1 to 14 of 14
| Analysis of charge trapping and breakdown mechanism in high-K dielectrics with metal gate electrode using carrier separation Cho, Byung Jin; Loh, WY; Joo, MS; Li, MF; Chan, DSH; Kwong, DL, International Electron Device Meeting (IEDM), pp.0 - 0, 2003-12-08 |
| Bipolar current stressing and electrical recovery of quasi-breakdown in thin gate oxides Cho, Byung Jin; Loh, WY; Li, MF; Xu, Z, 8th International Symp. on the Physical and Failure Analysis of Integrated Circuits (IPFA), pp.59 - 59, 2001-07-09 |
| Correlation between interface traps and gate laeakage in ultra-thin silicon dioxide Cho, Byung Jin; Loh, WY; Li, MF; Lek, CM; Yong, YF; Joo, MS, 9th International Symp. on the Physical and Failure Analysis of Integrated Circuits (IPFA), pp.246 - 246, 2002-07-08 |
| Dopant Segregated Pt and Ni-Germanide Schottky S/D p-MOSFETs with Strained Si-SiGe channel, 211th Electrochemical Society Meeting, SYMPOSIUM E1 Cho, Byung Jin; Zang, H; Chua, CK; Loh, WY, Electrochemical Society Meeting, SYMPOSIUM E1, 2007 |
| Dual Metal Gate Process by Metal Substitution of Dopant-Free Polysilicon on High-K Dielectric Cho, Byung Jin; Park, CS; Hwang, WS; Loh, WY; Tang, LJ; Kwong, DL, Symposium on VLSI Technology, pp.48 - 49, 2005-06-14 |
| Effects of Post-Decoupled-Plasma-Nitridation Annealing of Ultra-Thin Gate Oxide Cho, Byung Jin; Lek, CM; Loh, WY; Ang, CH; Lin, W; Tan, YL; Zhen, JZ; et al, 9th International Symp. on the Physical and Failure Analysis of Integrated Circuits (IPFA), pp.0 - 0, 2002-07-08 |
| GaAs Heteroepitaxy on SiGe-on-Insulator Using Ge Condensation and Migration Enhanced Epitaxy Cho, Byung Jin; Oh, HJ; Choi, KJ; Loh, WY; Htoo, T; Chua, SJ, Electrochemical Society Meeting, pp.0 - 0, 2007-05-06 |
| Improved current drivability and gate stack integrity using buried SiC layer for strained Si/SiGe channel devices Cho, Byung Jin; Zang, H; Loh, WY; Oh, HJ; Choi, KJ; Nguyen, HS; Lo, GQ, 211th Electrochemical Society Meeting, pp.0 - 0, 2007-05-06 |
| Integration of Dual Channels MOSFET on Defect-Free, Tensile-Strained Germanium on Silicon Cho, Byung Jin; Zang, H; Loh, WY; Ye, JD; Loh, TH; Lo, GQ, 2007 International Conference on Solid State Devices and Materials(SSDM), pp.0 - 0, 2007-09-18 |
| Integration of Tensile-Strained Ge p-i-n Photodetector on Advanced CMOS Platform Cho, Byung Jin; Wang, J; Loh, WY; Zang, H; Yu, MB; Chua, KT; Loh, TH, 4th International Conference on Group IV Photonics, pp.0 - 0, 2007-09-19 |
| New reliability issues of CMOS transistors with 1.3 nm gate oxide Cho, Byung Jin; Li, MF; Chen, G; Loh, WY; Kwong, DL, 7th International Symposium on Silicon Nitride and Silicon Dioxide Thin Insulating Films, pp.0 - 0, 2003-04-28 |
| Physical and electrical properties of MOCVD HfAlxOy gate dielectric and their composition ratio dependence Cho, Byung Jin; Joo, MS; Yeo, CC; Ching, YL; Loh, WY; Whoang, SJ; Mathew, S, International Conference on Materials for Advanced Technologies, pp.517 - 517, 2003-12-11 |
| Progressive breakdown statistics in ultra-thin silicon dioxides Cho, Byung Jin; Loh, WY; Li, MF; Chan, DSH; Ang, CH; Zhen, ZJ; Kwong, DL, 10th International Symp. on the Physical and Failure Analysis of Integrated Circuits (IPFA), pp.157 - 157, 2003-07-08 |
| The effect of Ge composition and Si cap thickness on hot carrier reliability of Si/Si1-xGex/Si p-MOSFETs with high-K/metal gate Cho, Byung Jin; Loh, WY; Majhi, P; Lee, SH; Oh, JW; Sassman, B; Young, C; et al, 2008 Symposium on VLSI Technology, pp.56 - 57, 2008-06-17 |
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