Scheduling of the stepper workstation for memory chips fabrication

Abstract

This thesis deals with a scheduling problem of minimizing turn-around-time (TAT) for a given throughput in memory chips fabrication. In memory chips fabrication, a wafer lot should reenter the photolithography workstation as many times as the number of the circuit layers. Among these layers, some layers called "critical layers" should be processed at the same machine (where the critical layer process was initiated on) for technological reasons. Thus, the routing of a wafer lot for processing all the critical layers is determined as the lot is allocated to a particular machine for processing its first critical layer. This thesis is technically concerned with such routing policy used in a production wafer fab. To minimize TAT, an optimal allocation of wafer lots to each photolithography machine should be determined. Under some assumptions the problem is converted to a single machine problem. Some solution properties of the converted problem are then characterized in a special deterministic environment, based upon which a simulation approach is derived to analyze the relationships between the allocation size and TAT.