Scheduling of the stepper workstation for memory chips fabrication메모리칩 제조를 위한 스테퍼 장비의 일정계획

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This thesis deals with a scheduling problem of minimizing turn-around-time (TAT) for a given throughput in memory chips fabrication. In memory chips fabrication, a wafer lot should reenter the photolithography workstation as many times as the number of the circuit layers. Among these layers, some layers called "critical layers" should be processed at the same machine (where the critical layer process was initiated on) for technological reasons. Thus, the routing of a wafer lot for processing all the critical layers is determined as the lot is allocated to a particular machine for processing its first critical layer. This thesis is technically concerned with such routing policy used in a production wafer fab. To minimize TAT, an optimal allocation of wafer lots to each photolithography machine should be determined. Under some assumptions the problem is converted to a single machine problem. Some solution properties of the converted problem are then characterized in a special deterministic environment, based upon which a simulation approach is derived to analyze the relationships between the allocation size and TAT.
Advisors
Sung, Chang-Supresearcher성창섭researcher
Description
한국과학기술원 : 산업공학과,
Publisher
한국과학기술원
Issue Date
1997
Identifier
112964/325007 / 000953125
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 산업공학과, 1997.2, [ ii, 57 p. ]

Keywords

Cyclic routing; Stepper; Critical layer; Group size; 그룹 크기; 순환 라우팅; 스테퍼; 중요회로층

URI
http://hdl.handle.net/10203/41493
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=112964&flag=dissertation
Appears in Collection
IE-Theses_Master(석사논문)
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