Heuristics for scheduling burn-in operations in a semiconductor test facility to minimize total tardiness

Abstract

In this thesis, we consider a scheduling problem in a semiconductor test facility, in which tardiness of orders is to be minimized. We focus on the loading/unloading workstation and the burn-in workstation, which may be considered bottleneck workstations in the test facility. In the loading/ unloading workstation, there are unrelated parallel machines, while there are identical parallel batch-processing machines called chambers in the burn-in workstation. Each chamber can process up to B boards simultaneously. A set of wafers is loaded on a board in the loading workstation, before a set of boards can be processed together in the burn-in workstation. We present four types of heuristic algorithms for scheduling problems in the burn-in workstations: extended list scheduling algorithms; look-ahead list scheduling algorithms; algorithms based on an existing heuristic developed for a single machine tardiness problem; and local search algorithms. Also, we develop several algorithms for the loading/unloading workstations. To evaluate performance of the algorithms, a series of computational experiments are performed on randomly generated test problems and results show that the suggested heuristic algorithms work well and outperform the existing rule currently used in a real system.