Acquisition behavior of a class of digital phase-locked loops

Abstract

In this thesis the acquisition behaviors of a class of first-and second-order digital phase-locked loops (DPLL) originally proposed by Reddy and Gupta have been studied in the absence of noise. Specifically, the acquisition time, the lock range, and the effects of quantization on acquisition behaviors have been investigated. It has been found that the number of quantization levels L and the number of phase error states N in modulo 2$\pi$ play important roles in acquisition. For a given L-level quantizer, as N increases, the acquisition time increases, but the lock range decreases. Also, the deviation of the steady state phase error decreases in this case. When the number of quantization levels L increases, the acquisition time decreases, and the lock range increases. However, variation of L affects little for the steady state phase error. The effects of loop filter characteristics on acquisition have also been considered. One can get a smaller acquisition time and a larger lock range as the filter parameter value becomes larger. However, the deviation of the steady state phase error increases in that case. In addition, the possibility of using a nonuniform quantizer for fast acquisition has also been studied. Analytical results have been verified by computer simulation and experiments.