(A) design and VLSI implementation of pipelined merge sorter

Abstract

The sorting operation which was regarded as a heavy load in computer application area, especially DBMS, is implemented into a specialized hardware VLSI chip so that more efficient sorting operation is guaranteed by. It is reported that the theoretical lower bound for sorting without a hardware parallelism is the time complexity of O(n $\log_2$ n) to sort n items. But it is also reported for that limit to be overcomed by using hardware parallelism. Then, our goal is to obtain the time complexity of O(n) with the size complexity of O ($\log_2$ n) using a hardware parallelism. For that goal, a two-way merge sorting is used for sorting algorithm and a pipelining is used for hardware parallelism. From those schemes, we developed a finite state machine which is adequate for the VLSI implementation of Pipelined Merge Sorter. For the layout of such a VLSI pipelined merge sorter, some floor-planning methods are introduced and estimated the effects on chip performance for each method and consider test problems of chip in aspect of functional test, manufacturing defect coverage by fault simulation.