(A) design and implementation of hardware sorters

Abstract

Sorting is a fundamental operation in data processing. Therefore specialized hardwares for the sort operation are adopted for fast processing. This thesis describes a taxonomy of this hardware sorter according to the environmental characteristics the data access characteristics and the representation of sort ordering. And the design and implementation of a systolic sorter and a pipeline merge sorter is introduced. The systolic sorter consists of a number of identical cells, which are connected as a form of two dimensional array. The systolic sorter has the size complexity of O($N^2$) and the time complexity of O(N). And a pipeline merge sorter which has more simple architecture than ever developed is designed and simulated. The simulation result indicates it has the same performance as the others in spite of its simple architecture. It has the time complexity of O(N) and the size complexity of O(longN). The time complexity of above two sorters indicates that those sorters can make the full use of the transfer time when used between hard disk and host computer. This thesis proves that in the case of using hardware sorter in database management system, the primitive data base operation such as projection, selection, join and set operation can be executed more effectively than without sorter.