DC Field | Value | Language |
---|---|---|
dc.contributor.advisor | Kyung, Chong-Min | - |
dc.contributor.advisor | 경종민 | - |
dc.contributor.author | Ahn, Young-Sub | - |
dc.contributor.author | 안영섭 | - |
dc.date.accessioned | 2011-12-14T02:12:26Z | - |
dc.date.available | 2011-12-14T02:12:26Z | - |
dc.date.issued | 1987 | - |
dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=65748&flag=dissertation | - |
dc.identifier.uri | http://hdl.handle.net/10203/39013 | - |
dc.description | 학위논문(석사) - 한국과학기술원 : 전기 및 전자공학과, 1987.2, [ 1책(면수복잡) ] | - |
dc.description.abstract | Program celled HIENA (Hierarchical Interactive Entry and Netlist Analysis) for schematic editing and extraction of electrical netlist has been developed to provide an integrated VLSI design environment based on EDIF under MS-DOS Version 3.0 on IBM PC AT. HIENA consists of three subprograms, SCHEMA, CONE, and HILINK; SCHEMA (SCHEMAtic editor) handles interactive schematic design entry and editing, and CONE (CONnectivity Extractor) extracts the connectivity information, i.e., netlist of each page drawn with SCHEMA, and HILINK (HIerarchical LINKer) is responsible for linking multiple pages with design hierarchy preserved and for providing the netlist information in EDIF format. | eng |
dc.language | eng | - |
dc.publisher | 한국과학기술원 | - |
dc.title | (A) hierarchical schematic capture system for VLSI design | - |
dc.title.alternative | VLSI 설계를 위한 계층적인 개략도 인식 시스템 | - |
dc.type | Thesis(Master) | - |
dc.identifier.CNRN | 65748/325007 | - |
dc.description.department | 한국과학기술원 : 전기 및 전자공학과, | - |
dc.identifier.uid | 000841185 | - |
dc.contributor.localauthor | Kyung, Chong-Min | - |
dc.contributor.localauthor | 경종민 | - |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.