Time-based RF sampling bandpass ADC using voltage-controlled oscillators

Abstract

In this paper, a bandpass ADC based on time-interleaved oversampled ADC is introduced. Unlike previous delta-sigma bandpass ADCs that require accurate DACs and high speed analog circuits, the proposed architecture provides bandpass function by time-interleaving 1st-order VCO-based ADCs. The use of VCO-based ADC has the advantage that its resolution is determined by the time-resolution rather than the voltage resolution, thus making it attractive for future low-voltage CMOS processes. The performance of the proposed ADC is theoretically analyzed and simulated in ideal condition as well as in non-ideal condition, in the presence of non-linearity, sampling clock jitter and mismatch. A prototype is implemented in CMOS 65nm technology. The ADC has 8 time-interleaved channels with their sampling frequency of 500MHz, thereby achieving the effective sampling frequency of 4GHz. The measurement results show the maximum SNR of 63.3dB at 1MHz of bandwidth whereas the maximum SNDR is limited due to spurious tones from timing mismatch. The total power consumption of the ADC is 20mW and 6.7pJ/conversion-step of FOM is achieved.