Owing to the continually shrinking feature sizes, the higher clock frequencies, and the simultaneous growth in complexity, the problem of saving clock network power is getting formidable task. In modern VLSI circuits with power dissipation, the clock tree uses at least 30% of the total power and may even reach 50%. In the design of low power VLSI circuits, both dual-edge-triggered flip-flop (DETFF) and clock gating can be used in order to save clock network power of the circuits.
The main advantage of using DETFF is that it can support constant data throughput with only half the clock frequency, and clock gating can reduce the clock power by shutting off clocks to circuits that are not being used. Since DETFF implementations hardly have symmetric timing characteristics, DETFF-based circuits cause more timing loss and more complex timing analysis than conventional single-edge-triggered flip-flop (SETFF).
At the first part of this work, I proposed static timing analysis method for DETFF-based circuits with clock gating. At the second part, duty-ratio optimization method is proposed, so that timing loss of DETFF-based circuits with clock gating can be minimized.