Efficient hardware architecture for mode decision in H.264/MPEG-4 AVC encoder

Abstract

H.264/MPEG-4 AVC is the most outperforming video standards with a lot of helpful coding tools. However it takes huge amount of computational complexity and memory access especially in mode decision procedure, intra and inter prediction which makes it difficult to design a hardware encoder architecture for real-time encoding for high-quality specification. In this paper, we proposed architecture for efficient mode decision in H.264/MPEG-4 AVC Encoder for SDTV specification. The proposed IME hardware adapts zig-zag scan for full data reuse and SAD adder tree for fast one-access 4×4 SAD generations. Novel FME architecture also proposed in this paper by applying data reuse and parallel fractional pel generation. It also proposed unified intra predictor generator which is especially efficient for I16MB plane mode without any additional hardware. Based on proposed mode decision engine, this paper proposed 3-stage pipelined mode decision architecture which can share the reference and current pels SRAMs. The whole architecture can process SDTV (720 × 480) 4:2:0 30 Hz video in real time, at the operating frequency of 130MHz. The transistor count is 132K, and the core size is 2.2 mm × 2.2 mm under Samsung 0.18-μm CMOS technology.