As demand for multi functional and high quality devices has been increasing rapidly, image compression standards is getting more strong compression factor with better image quality characteristics. JPEG2000 has been the new solution alternating the JPEG. JPEG2000 adopts the DWT as the frequency converter and compounded of multiple coding algorithms as the entropy coding, named “EBCOT”. But the EBCOT accesses the DWT result by the bit-plane order. That is the obstacle in many ways; memory access and intermediate buffer problem, and throughput. The fast and approximate method co-works together with a high performance EBCOT module for rate control. Among the efficient hardware researches about JPEG2000, proposed architecture is one of the simplest and accomplishes the immediate processing time saving. The proposed architecture discards the EBCOT process of bit-plane which will be eliminated in the rate control function. With this technique, it can be possible to improve the 9% ~27% of processing time when EBCOT hardware is running. And also, it improves more than 25% of processing time when rate control software is running. The additive logic is very small, and also is not affect the critical delay. Moreover, image is little degraded because the eliminated bit-planes is the real candidates to discard by rate control function. The proposed architecture is implementation in Verilog HDL and synthesized in Samsung 0.18um technology. The operating frequency is 133MHz.