Effect of power supply imbalance on NF of CMOS low noise amplifier for UHF RFID applications

Abstract

These days, there have been many efforts to integrate every parts of system, as a kind of RF, power amplifier, analog and digital circuits, in a system, which called a mixed-mode system. The integration makes the system has low cost and high integration features. However, it also gives many signal integrity and power integrity problems. Especially, power/ground noise due to coupling of digital circuit switching noise or coupling of digital clock signal degrades the performance of RF circuits such as gain, linearity, noise figure. In case of LNA, the noise figure (NF) is the one of the most important performance factor because the noise figure of receiver front-end system is dominated by the noise figure of LNA. If the noise figure of LNA is degraded by the power/ground noise, it directly degrades the noise figure of the receiver front-end. Then, the noise figure of receiver front-end determines the sensitivity of that. Finally, the power/ground noise on LNA degrades the performance of whole receiver front-end. To avoid the degradation, it is important to expect and simulate the effect of the power/ground noise on noise figure during the system designing process. In this paper, noise figure degradation of CMOS low noise amplifier for UHF RFID application, which is caused by power/ground noise from power supply imbalance is analyzed. Then, a modified noise figure formula to estimate the effect of power/ground noise from power supply imbalance is proposed. Because the power supply imbalance is caused by package power/ground distribution network (PDN) design, package PDN is modeled with balanced TLM method. Also, the on-chip PDN and equivalent circuit of LNA is modeled to simulate the modified noise figure. The modified noise figure formula is verified by measurement. It shows 100mVpp power/ground noise at package power/ground degrades about 120dB of noise figure at differential LNA output.