(A) 0.18um CMOS 10 Gb/s 1:4 DEMUX and 5 GHz PLL using fast locking scheme = 0.18um CMOS 공정을 이용한 10 Gb/s 1:4 DEMUX와 빠른 locking 방법을 이용한 5GHz PLL

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The computing performance of a single chip has increased exponentially due to the advance of semiconductor technology. Accordingly, the improvement of I/O bandwidth is indispensable. High-speed serial data links provide multi-gigabit bandwidth with reduced system complexity and cost. DEMUX is key component of these data communications at receiver. It reduces the burden of receiver for high speed operation. High speed serial input data is de-multiplexed to low speed parallel output data for effective data process in receiver. Proposed DEMUX is simulated under 0.18um CMOS process, and its data rate is 10 Gb/s. Proposed DEMUX uses the improved current mode logic (CML) and replica bias circuits for high speed, low power consumption, and correct operation. This proposed DEMUX can be used at optical fiber link. Next, PLL for fast locking time is proposed. A PLL is a frequency synthesizer which produces high frequency from external low frequency. Locking time is one of characteristics of PLL performance. For portable or mobile applications, locking time is very important since the PLL must support fast entry and exit from power management techniques. In addition, if a PLL is used at the clock interface of a microprocessor and the system is powered down frequently to save energy, it becomes critical to know how long the system must remain idle after it is turned on to allow adequate phase alignment between the external and internal clocks. Thus, fast locking PLL scheme will be introduced in this paper. Proposed PLL is simulated under 0.18um CMOS process, and target frequency is 5 GHz. Proposed PLL is used frequency adjustment scheme, which consist of frequency difference detector, phase difference detector, and multiplexer for control charge pump bias voltage. The process of proposed DEMUX and PLL is a 0.18um CMOS logic. In proposed DEMUX, data rate is 10 Gb/s and power consumption is 12.24mW at 1.8V supply voltage and typical-typical state. Its area of layout is...
Advisors
Kim, Lee-Supresearcher김이섭researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2006
Identifier
255560/325007  / 020043663
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학전공, 2006.2, [ vi, 58 p. ]

Keywords

PLL; 1:4 DEMUX; fast locking 10Gb/s; 빠른 락킹; 프리컨시 합성; 디먹스

URI
http://hdl.handle.net/10203/38391
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=255560&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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