Design and implementation of high-speed CMOS clock and data recovery circuit for optical interconnection applications

Abstract

A 4-Gb/s clock and data recovery (CDR) circuit is realized in a 0.25-㎛ standard CMOS technology. The CDR circuit exploits 1/8-rate clock technique to facilitate the design of a voltage-controlled oscillator (VCO) and to eliminate the need of 1:4 demultiplexer, thereby achieving low power consumption. The VCO incorporates the ring oscillator configuration with active inductor loads, generating four half-quadrature clocks. The VCO control line comprises both a programmable 6-bit digital coarse control and a folded differential fine control through a charge-pump and a low pass filter. Duty-cycle correction of clock signals is obtained by exploiting a high CMRR (common-mode rejection ratio) differential amplifier at the ring oscillator output. A 1/8-rate linear phase detector accomplishes the phase error detection with no systematic phase offset and inherently performs the 1:4 demultiplexing. Test chips demonstrate the jitter of the recovered clock to be 5.2ps RMS and 47ps pk-pk for $2^{31}-1$ pseudo random bit sequence (PRBS) input data. The phase noise is measured to be -112dBc/Hz at 1MHz offset. The measured bit error rate (BER) is less than 10-6 for $2^{31}-1$ PRBS. The chip excluding output buffers dissipates 70mW from a single 2.5-V supply.