Design and implementation of high-speed CMOS clock and data recovery circuit for optical interconnection applications = 광 연결 응용을 위한 고속 CMOS 클럭과 데이터 복원 회로의 설계 및 구현

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A 4-Gb/s clock and data recovery (CDR) circuit is realized in a 0.25-㎛ standard CMOS technology. The CDR circuit exploits 1/8-rate clock technique to facilitate the design of a voltage-controlled oscillator (VCO) and to eliminate the need of 1:4 demultiplexer, thereby achieving low power consumption. The VCO incorporates the ring oscillator configuration with active inductor loads, generating four half-quadrature clocks. The VCO control line comprises both a programmable 6-bit digital coarse control and a folded differential fine control through a charge-pump and a low pass filter. Duty-cycle correction of clock signals is obtained by exploiting a high CMRR (common-mode rejection ratio) differential amplifier at the ring oscillator output. A 1/8-rate linear phase detector accomplishes the phase error detection with no systematic phase offset and inherently performs the 1:4 demultiplexing. Test chips demonstrate the jitter of the recovered clock to be 5.2ps RMS and 47ps pk-pk for $2^{31}-1$ pseudo random bit sequence (PRBS) input data. The phase noise is measured to be -112dBc/Hz at 1MHz offset. The measured bit error rate (BER) is less than 10-6 for $2^{31}-1$ PRBS. The chip excluding output buffers dissipates 70mW from a single 2.5-V supply.
Advisors
Yoo, Hoi-Junresearcher유회준researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2004
Identifier
238440/325007  / 020013301
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학전공, 2004.2, [ 46 p. ]

Keywords

OPTICAL INTERCONNECTION; OPTICAL RECEIVER; CMOS; CLOCK AND DATA RECOVERY CIRCUIT; 1/8-RATE CLOCK; 1/8 배 클럭; 광 연결; 광수신기; 상보성금속산화반도체; 클럭과 데이터 복원 회로

URI
http://hdl.handle.net/10203/37763
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=238440&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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