Tiling-based polygon rasterizer with dynamic stamp positioning = 동적인 스탬프 위치를 이용한 타일기반 폴리곤 래스터라이저

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The demand on the 3D graphics is rapidly increasing. Game and virtual reality require more 3D graphics performance, so 3D graphics is becoming one of important technologies these days. For the last 10 years, we have achieved so much improvement but we still have a long way to go. Nowadays we talk about the photorealism. Many researches have been done on this subject. More bits on fragment parameters, more textures, and putting pixel shader and vertex shader for more programmability are popular approaches to photorealistic scenes. At the same time object models are getting smaller to describe models in detail. Tiling-based edge function traversal is a popular algorithm used in rendering. But, it has some overhead in traversing polygons, like visiting non-productive pixels, which does not have any valid pixel. It spends significant rendering time when processing small polygons. As polygons are getting smaller for photorealistic scenes, the system requires faster rasterizer which can process small polygons. In this paper, we proposed the dynamic positioning polygon rasterizer which can improve the throughput in rendering polygons, especially pixel-sized polygons. In existing tiling based edge function polygon rasterizer, a stamp, which is used to find valid pixels in a polygon, is aligned to the tile boundary. And stamps only can move to the fixed stamp positions. So, a polygon covering multiple stamp positions can be rendered by visiting all stamp positions. The rendering time is in proportion to the number of tiles touched by a polygon. If a polygon is smaller enough to be covered by a stamp, the rendering time can be reduced by stamping that polygon directly without visiting all covered stamp positions. In the proposed architecture, a stamp can be positioned on the arbitrary positions. So a polygon which is fit into one dynamic stamp can be rendered in one clock. In this paper, we proposed proper hardware architecture with this scheme. And we calculated the req...
Advisors
Kim, Lee-Supresearcher김이섭researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2003
Identifier
180537/325007 / 000983586
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학전공, 2003.2, [ vi, 59, [4] p. ]

Keywords

3D graphics; rasterizer; polygon; 폴리곤; 삼차원 그래픽스; 래스터라이저

URI
http://hdl.handle.net/10203/37701
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=180537&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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