(A) design of bus activity monitoring logic for SOC prototyping system = 시스템칩 프로토타이핑 시스템을 위한 버스 모니터링 로직의 설계

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dc.contributor.advisorKyung, Chong-Min-
dc.contributor.advisor경종민-
dc.contributor.authorLee, Sang-Heon-
dc.contributor.author이상헌-
dc.date.accessioned2011-12-14T01:52:09Z-
dc.date.available2011-12-14T01:52:09Z-
dc.date.issued2003-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=180529&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/37693-
dc.description학위논문(석사) - 한국과학기술원 : 전기및전자공학전공, 2003.2, [ iv, 58 p. ]-
dc.description.abstractIn functional prototyping, which is need for verifying the functional correctness of complex System-on-a-Chip(SOC), debugging is sometimes difficult due to the lack of probing port and internal logic analyzer for observing and correcting the internal signals. To overcome this limitation, a monitoring logic dedicated to the bus architecture is imbedded in the prototyping system to provide a well-defined and compacted information of the bus activity to system designers. Although there are several works on SOC bus monitoring logic, they are IP-dependent or simulation-targeted, and, therefore, is not generally applicable for the prototyping of a bus-based SOC. In this thesis a monitoring logic which is appropriate to prototyping system and independent of the components of SOC is designed. AMBA AHB is chosen as bus architecture. The monitoring logic designed in this thesis stores the information of the bus activity in three words(12 bytes) for each transaction. The data includes master, slave, start address, read/write, burst length, transfer size, ending condition, time spent in waiting grant, time stamp. The data captured is transferred to the host system via PCI interface at real-time. Experimental result shows how bus arbitration scheme affects the characteristic of operation of the system.eng
dc.languageeng-
dc.publisher한국과학기술원-
dc.subjectmonitor-
dc.subjectSOC-
dc.subject시스템칩-
dc.subject버스 모니터-
dc.subjectAMBA AHB-
dc.title(A) design of bus activity monitoring logic for SOC prototyping system = 시스템칩 프로토타이핑 시스템을 위한 버스 모니터링 로직의 설계-
dc.typeThesis(Master)-
dc.identifier.CNRN180529/325007-
dc.description.department한국과학기술원 : 전기및전자공학전공, -
dc.identifier.uid020013427-
dc.contributor.localauthorKyung, Chong-Min-
dc.contributor.localauthor경종민-
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EE-Theses_Master(석사논문)
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