(A) design of bus activity monitoring logic for SOC prototyping system

Abstract

In functional prototyping, which is need for verifying the functional correctness of complex System-on-a-Chip(SOC), debugging is sometimes difficult due to the lack of probing port and internal logic analyzer for observing and correcting the internal signals. To overcome this limitation, a monitoring logic dedicated to the bus architecture is imbedded in the prototyping system to provide a well-defined and compacted information of the bus activity to system designers. Although there are several works on SOC bus monitoring logic, they are IP-dependent or simulation-targeted, and, therefore, is not generally applicable for the prototyping of a bus-based SOC. In this thesis a monitoring logic which is appropriate to prototyping system and independent of the components of SOC is designed. AMBA AHB is chosen as bus architecture. The monitoring logic designed in this thesis stores the information of the bus activity in three words(12 bytes) for each transaction. The data includes master, slave, start address, read/write, burst length, transfer size, ending condition, time spent in waiting grant, time stamp. The data captured is transferred to the host system via PCI interface at real-time. Experimental result shows how bus arbitration scheme affects the characteristic of operation of the system.