Design and Implementation of high performance application specific memory

Abstract

In this thesis, the high performance memory architectures for specific applications, especially 3D graphics and network were investigated and some of them were implemented. In the sphere of 3D graphics, large memory bandwidth is required to process real-time high-quality image. And embedded memory architecture is a good approach for high bandwidth and low power operations. The embedded memory architectures for 3D graphic engine are designed and implemented using 0.16um DRAM technology as a part of the RamP-IV processor which is designed for the mobile applications. For the rendering engine in the chip, three kinds of memory were integrated, which are frame buffer, Z-buffer and texture memory. Each of them are optimized for the rendering engine to have maximum performance by supplying one-clock operation, variable clock operation and partial activation scheme. In the network application, quick-search of the lookup table is one of the important issue. In the previous work, trie search with embedded memory is used. However this method requires many clock cycle to search the desired data. To perform the operation with one-cycle, Content Addressable Memory (CAM) is preferred in search engine. But conventional CAM cell consumes large area and enormous power. To solve these problems, a new CAM cell and match line architecture were proposed and simulated using 0.35um CMOS logic technology. The proposed cell is able to store ternary value with small increase of area. Using the cell, the length of the match line is reduced to half size compared to conventional cell architecture, which means that search is faster than that of conventional architecture.