Simulation speedup for supersaclar processors using sample-data = 표본 데이터를 이용한 슈퍼스칼라 프로세서의 시뮬레이션 시간 개선

Cited 0 time in webofscience Cited 0 time in scopus
  • Hit : 199
  • Download : 0
In the current processor design, there are various processor configurations. Generally, a designer tries to find target processor configurations to satisfying target performance with minimum hardware cost. The performance evaluation is done through cycle-by-cycle simulation in an early design phase. Unfortunately, this evaluation traditionally involves the use of costly full trace simulations, which is time- and space-consuming task. This thesis proposes a fast and accurate estimation method for execution cycles of a program, and provides a designer with the reliable estimation. For this approach, we consider some characteristics of a program. First, a program structure consists of basic blocks and control flows. They are never changed by processor configurations. Therefore, each basic block execution counts are independent on processor configurations. Second, the execution cycles of basic blocks depend on them. Third, each basic block is iteratively executed by the loops in a program, which have the constant execution cycles. When processor configurations are varied, we reuse the basic block execution counts information and obtain the execution cost information of basic blocks through sample data simulation. The basic block execution counts and execution cycles are classified by both predecessor and cache/branch predictions misses of the current basic block for making the accurate estimation model. The total execution cycles of a program is determined by the form of weighted-sum between execution counts and cost of basic blocks. Therefore, we can estimate total execution cycles of a program in a relatively short time using this approach. There is an inevitable estimation error due to the information loss by using sample data simulation. Therefore, we provide worst-case error which may occur in the process of estimation. A designer can obtain estimation result within desired error by using it. The worst-case error is smaller than measured error which is the dif...
Advisors
Kim, Tag-Konresearcher김탁곤researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2003
Identifier
180498/325007 / 020013592
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학전공, 2003.2, [ x, 58 p. ]

Keywords

sample-data simulation; estimation of execution cycles; Simulation SpeedUp; architecture simulatior; 아키텍터 시뮬레이터; 표본데이터 시뮬레이션; 수행시간 추정; 시뮬레이터 시간개선

URI
http://hdl.handle.net/10203/37666
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=180498&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
Files in This Item
There are no files associated with this item.

qr_code

  • mendeley

    citeulike


rss_1.0 rss_2.0 atom_1.0