(An) area-efficient 8K/4K/2K-point pipelined FFT processor

Abstract

The pipelined FFT processor is the key component in OFDM receiver. In order to optimize the area of the pipelined FFT processor, area of combinational logic, especially complex multiplier and memory element must be minimized. In this theis, a area efficient pipelined FFT processor has been presented. Area reduction mainly comes from complex constant multiplier that is introduced by 4-level index mapping. The stage, which consists of constant muliplier, could operate without ROM storing twiddle factor. To verify and optimize the proposed FFT processor, C-level language has been developed. The FFT processor has progressive wordlength with stage and 13-bi twiddle factors that is resulted in various simulations. A proposed FFT processor has 25.1% smaller combinational logic area and 23.1% smaller ROM than $R2^2SDF$ that is the most resource efficient pipeline architecture proposed previously. Also, proposed FFT processor has low power characteristic by accessing the ROM efficiently and using constant multiplier.