(An) area-efficient 8K/4K/2K-point pipelined FFT processor = 저면적 8K/4K/2K-point 파이프라인 방식의 FFT 프로세서의 설계

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The pipelined FFT processor is the key component in OFDM receiver. In order to optimize the area of the pipelined FFT processor, area of combinational logic, especially complex multiplier and memory element must be minimized. In this theis, a area efficient pipelined FFT processor has been presented. Area reduction mainly comes from complex constant multiplier that is introduced by 4-level index mapping. The stage, which consists of constant muliplier, could operate without ROM storing twiddle factor. To verify and optimize the proposed FFT processor, C-level language has been developed. The FFT processor has progressive wordlength with stage and 13-bi twiddle factors that is resulted in various simulations. A proposed FFT processor has 25.1% smaller combinational logic area and 23.1% smaller ROM than $R2^2SDF$ that is the most resource efficient pipeline architecture proposed previously. Also, proposed FFT processor has low power characteristic by accessing the ROM efficiently and using constant multiplier.
Advisors
Park, In-Cheolresearcher박인철researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2003
Identifier
180466/325007 / 020013209
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학전공, 2003.2, [ iv. 48 p. ]

Keywords

Pipelined FFT processor; DVB-T; 파이프라인 FFT 프로세서; OFDM

URI
http://hdl.handle.net/10203/37635
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=180466&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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