Design and optimization of geometry acceleration for portable 3D graphics = 휴대용 3D Graphics를 위한 기하 연산 가속기의 설계 및 최적화

Cited 0 time in webofscience Cited 0 time in scopus
  • Hit : 235
  • Download : 0
In this thesis, the efficient interface logic for multimedia processing, named as the bandwidth equalizer (BEQ) was implemented as a part of RAMP-IV (Ram Processor IV) mobile multimedia processor with 0.16㎛ DRAM process. To reduce the communication cost and power consumption, BEQ uses the adaptive flow control with delayed activation and partial word-line activation schemes. To achieve the further efficient memory utilization, the internal 1KB dual-port SRAM is used as a scratch pad memory of main processor. With flow control, BEQ shows 3.5㎽ power consumption while preventing CPU interrupts for typical test cases. To realize the real time 3D graphics in mobile applications, the optimal architecture of 3D geometry processing unit was analyzed by simulating the 3D applications on the various advanced RISC machines (ARM) processor platforms which are the main processor of RAMP-IV system. From the system level analysis, the mobile graphics library (MobileGL) based on OpenGL specification was developed with fixed point arithmetic operations optimized to architecture of ARM processors. MobileGL shows the 150K vertices/sec geometry performance that is suitable for mobile devices such as personal digital assistants (PDA). For better performance enhancement for RAMP-IV processor, the 3D geometry coprocessor, SATINE, was proposed to accelerate the geometry operations. The SATINE coprocessor has the 4 way 128 bit integer SIMD unit optimized for the 3D operations in the datapath instead of vector floating point unit for the low cost and high performance. The stream processing and script execution were used to maximize the performance of computation for the vertex data of 3D geometry model. The master request interface (MRI) was designed to obtain the parallel utilization of two datapaths of the main processor and coprocessor. The proposed architecture shows the 1.67M vertices/sec and 400K vertices/sec polygon calculation rates for the un-lit and lit model, respectively at ...
Yoo, Hoi-Junresearcher유회준researcher
한국과학기술원 : 전기및전자공학전공,
Issue Date
180453/325007 / 020013294

학위논문(석사) - 한국과학기술원 : 전기및전자공학전공, 2003.2, [ [v], 67 p. ]


Portable; Geometry; 3D Graphics; Optimization; 최적화; 휴대용; 기하연산; 3D 그래픽스

Appears in Collection
Files in This Item
There are no files associated with this item.


  • mendeley


rss_1.0 rss_2.0 atom_1.0