Design and implementation of a 80Gbps shared bus packet switch using embedded DRAM

Abstract

In this paper several methods to use eDRAM (embedded DRAM, on-chip DRAM) in packet switches are analyzed. A practical method using eDRAM as an output queue is proposed especially in a shared bus packet switch. In the newly proposed output buffer architecture, hierarchical output buffer (HOB), SRAM plays a role of the small FIFO buffer between a high-speed shared bus and a large eDRAM output buffer. The high density of eDRAM can provide larger capacity than static memories, which results in lower packet loss probability. This paper shows the performance analysis on the proposed HOB switch of 8 ports with the port speed of 10Gbps for 10 Gigabit Ethernet or OC-192c standards. We determine two optimal configurations of hierarchical output buffer by simulation. One is focused on area reduction issue and the other on reduction of cell loss probability. First one achieve the cell loss probability of $10^{-6}$ and second one does that of $10^{-8}$ at 90% offered load under real trace traffic of IP packets. About 2 times area reduction is obtained by using hierarchical and hybrid output buffer rather than SRAM buffer. A prototype chip has been designed and implemented by using 0.16um DRAM-based SoC technology. During the chip implementation, Both-Side I/O scheme is proposed to double the I/O data bits of eDRAM. The die area is 4mm × 9mm including input generation block. This chip has taped out in May 2002, and is under fabrication up to now.