3D Graphics rendering processor using out-of-order memory access비순차적 메모리 접근을 이용한 삼차원 그래픽스 렌더링 프로세서

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As the 3D graphics demand grows, the hardware accelerator dedicated to 3D graphics algorithms becomes popular. Recently, commodity graphics processors have rendered hundreds of million pixels, but more improvement is still required to render photo-realistic scenes at real-time rates. The factor to limit the growth of 3D graphics rendering performance is memory bandwidth, because there is no temporal locality to make cache effective in 3D graphics pipeline. In this paper, approach to increase efficiency of memory bandwidth as is proposed. Precharging time and row-activating time is much longer than data cycle time in DRAM-based memory. Since address scheduling chunks the addresses in the same row, it reduces the turn-around cycle of DRAM. Polices adequate to graphics system are suggested and analyzed in this paper. Out-of-order fragment processing architecture is also proposed with out-of-order memory access. In graphics system, the data ready first can be processed first, owing to rare dependency between fragments. Out of order fragment processing does not enforce the fragment whose all data are fetched on waiting to be served even if earlier fragments are not processed. This requires no reorder buffer and shortens the amount of in-flight fragments to be stored in order to avoid pipeline stall. Additionally, dedicated texel fetch unit architecture is suggested in this paper. Close pixels in screen a lso have the very high locality in texture space owing to mip-map structure. Texel size can be almost same to pixel size by selecting adequate level-of-detail, and some texture filtering algorithms need many texels adjacent to footprint center. Therefore the several same texel may be needed by neighboring pixel. Fetching redundant texel requests at once reduces cache access and makes one port cache operate just as multi-port cache. A texel fetch unit combines arrived requests with pending requests if their addresses are equal. A texel cache must not stall requ...
Advisors
Kim, Lee-Supresearcher김이섭researcher
Description
한국과학기술원 : 전기및전자공학전공,
Publisher
한국과학기술원
Issue Date
2002
Identifier
174086/325007 / 020003063
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학전공, 2002.2, [ v, 54, [4] p. ]

Keywords

memory access scheduling; graphic processor architecture; out-of-order process; 비순차적 처리; 메모리 접근 스케쥴링; 그래픽 프로세서 구조

URI
http://hdl.handle.net/10203/37556
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=174086&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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