IP 설계 지침서 제안 및 EML용 processor core IP 의 설계 및 구현Design and implementation of processor core IP and suggestion of IP design guideline

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DC FieldValueLanguage
dc.contributor.advisor유회준-
dc.contributor.advisorYoo, Hoi-Jun-
dc.contributor.author한진호-
dc.contributor.authorHan, Jin-Ho-
dc.date.accessioned2011-12-14T01:48:52Z-
dc.date.available2011-12-14T01:48:52Z-
dc.date.issued2001-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=169407&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/37485-
dc.description학위논문(석사) - 한국과학기술원 : 전기및전자공학전공, 2001.8, [ ix, 78 p. ]-
dc.languagekor-
dc.publisher한국과학기술원-
dc.subjectSOC(System On a Chip)-
dc.subjectEML(Embedded Memory Logic)-
dc.subjectIP 설계 지침서-
dc.subjectIntellectual Properties-
dc.subjectEmbedded Processor-
dc.subjectVSIA-
dc.subjectVCX-
dc.subjectProcessor Core-
dc.subjectIP Design Guideline-
dc.titleIP 설계 지침서 제안 및 EML용 processor core IP 의 설계 및 구현-
dc.title.alternativeDesign and implementation of processor core IP and suggestion of IP design guideline-
dc.typeThesis(Master)-
dc.identifier.CNRN169407/325007-
dc.description.department한국과학기술원 : 전기및전자공학전공, -
dc.identifier.uid000983632-
dc.contributor.localauthor유회준-
dc.contributor.localauthorYoo, Hoi-Jun-
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EE-Theses_Master(석사논문)
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