Performance analysis of gigabit ethernet shared-memory switch with embedded DRAM

Abstract

As the line-rate of the Ethernet becomes 1Gbps and more than that, the demand for the high-performance switch is increasing. Further more, the bursty traffic pattern of multimedia data demands the switches to have larger memory capacity. Therefore, DRAM, especially embedded-DRAM, is emerging as a good candidate to replace SRAM buffers. The performance analyses of various kinds of switches have been reported. However, they assumed that the bandwidth of the memory is constant. When the DRAM is used as a memory, however, the bandwidth depends on the access pattern. Therefore, to evaluate the performance of the embedded DRAM shared-memory switch, the characteristics of DRAM must be concerned. In this work, the DRAM is applied as a shared-memory. And the performance analysis of the shared-memory switch is performed when the various control schemes are applied. The dedicated policies for the address issuing and service port selection are proposed and the performance of the switch with the dedicated polices is simulated. As a result, the maximum throughput of the 8 port shared-memory switch with embedded-DRAM showed 0.82 with fully offered-load, and that is 15% degradation compared with that of SRAM`s. The capacity of shared-memory was 2Mbit with completely sharing. The input packet arrival is assumed to follow Poisson distribution. The real world sampling data is adopted for the input packet size distribution.