Jitter-reduced digital symbol timing recovery for 16-CAP VDSL system

Abstract

This thesis presents a method to extract the symbol timing with the jitter reduction for a VDSL system employing 16-CAP modulation scheme. The proposed jitter reduction method is based on the gear-shifting algorithm in MMSE criterion, and applied to the symbol timing recovery based on the digital spectral line method. The proposed algorithm consists of two independent controls of the loop gain: One is to decrease the loop gain regardless of the loop error sequence and the other is to increase the loop gain by estimating the timing error from the loop error sequence. The proposed jitter reduction algorithm overcomes the poor timing jitter performance shown in the digital spectral line method and improves the convergence speed. Simulation results show that the timing is recovered within 400 symbols and the timing jitter is less than 0.4% of the symbol period at the worst case. As a result, the BER is less than $10^{-12}$ under the reference loop condition and this performance shows that the digital spectral line method with the proposed jitter reduction algorithm is appropriate to the DAVIC 16-CAP VDSL system.