Interface scheme for high-speed synchronous-DRAM

Abstract

This paper describes a new interface scheme for a high performance, especially focused on an improvement of the timing margin, synchronous DRAM (SDRAM), which can be used as a part of an internal clock generation block of the SDRAM. For this scheme, a simple protocol is defined and its processing unit is proposed. The defined protocol is adopted to provide a skew information between the edges of the transmitted data and a reference clock, and to control a sampling window mismatch. The protocol-processing unit is used to estimate and encode the skew of the each of parallel-transmitted data based on the proposed protocol, which is made up of a phase-locked loop (PLL), a skew estimation block, register files, and control blocks. Consequently, by compensating the skew of each data line according to the output of a protocol-processing unit, the skew among the data can be reduced to 1/8 clock-cycle ideally, for the dispersed data edges over 1 clock period through the transmission lines. It connotes that timing-margin between signals is improved. So, a stable data acquisition is allowed to 800 Mb/s data rates. This scheme may be employed to an interface part of a high-speed parallel data transceiver, in which the skew between signals should be considered.