(A) design of low power floating-point arithmetic units

Abstract

The demand for high performance,Low Power floating point unit has been on the rise during the recent years. Recently, in multimedia and portable system, fast and accurate co-processor for scientific application, DSP and Signal Processing is needed. and also the Low power consumption is necessay because the battery is developed very slowly, twice battery performance per ten year. In this thesis the Floating-Point Arithmetic units, Adder/Subtractor and Multiplier/Divider which are frequenlty used in many applications and consumes much power,than Square Root and remainder. I will focus on the ALU that is designed to have multiple path according to the characteristics of the operands and to have small area. And Multiplier with radix-4 modified booth algorithm and divider with radix-4 SRT algorithm are designed to consume less power and have small area.