(A) design of fast RSA cryptographic processor = 고속 RSA 암호프로세서의 설계

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The RSA cryptographic systems require modular exponentiation, which binary or m-ary methods can break into a series of modular multiplications. Montgomery``s modular multiplication is known as a fast modular multiplication algorithm that avoids the division needed to take the modulo reduction. In this thesis, a single-chip 1024-bit RSA processor is designed and implemented in register transfer level using Montgomery modular multiplication algorithm. To achieve high throughput, the pipelined radix-4 booth multiplier which accepts two multiplicands, two multipliers, and an addend as input is employed. The performance is estimated as 80kbit/s for 1024-bit words, resulting in a fast RSA cryptographic processor compared with the previous cryptographic processors.
Advisors
Park, In-Cheolresearcher박인철researcher
Description
한국과학기술원 : 전기및전자공학과,
Publisher
한국과학기술원
Issue Date
1998
Identifier
134829/325007 / 000963238
Language
eng
Description

학위논문(석사) - 한국과학기술원 : 전기및전자공학과, 1998.2, [ v, 45 p. ]

Keywords

Cryptographic processor; RSA algorithm; High speed; 고속; 암호프로세서; RSA 알고리즘

URI
http://hdl.handle.net/10203/37046
Link
http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=134829&flag=dissertation
Appears in Collection
EE-Theses_Master(석사논문)
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