(A) design of fast RSA cryptographic processor

Abstract

The RSA cryptographic systems require modular exponentiation, which binary or m-ary methods can break into a series of modular multiplications. Montgomery``s modular multiplication is known as a fast modular multiplication algorithm that avoids the division needed to take the modulo reduction. In this thesis, a single-chip 1024-bit RSA processor is designed and implemented in register transfer level using Montgomery modular multiplication algorithm. To achieve high throughput, the pipelined radix-4 booth multiplier which accepts two multiplicands, two multipliers, and an addend as input is employed. The performance is estimated as 80kbit/s for 1024-bit words, resulting in a fast RSA cryptographic processor compared with the previous cryptographic processors.