100BaseT4 이더넷 송수신기를 위한 타이밍 복원 회로의 설계Timing recovery circuit design for 100BaseT4 ethernet transceiver
- Advisors
- 김범섭researcher; Kim, Beom-Supresearcher
- Description
- 한국과학기술원 : 전기및전자공학과,
- Publisher
- 한국과학기술원
- Issue Date
- 1997
- Identifier
- 114245/325007 / 000953476
- Language
- kor
- Description
학위논문(석사) - 한국과학기술원 : 전기및전자공학과, 1997.2, [ v, 52 p. ]
- Keywords
디지탈 PLL; 이더넷 송수신기; 타이밍 복원; PLL; DPLL; Timing recovery; Ethernet; 100BaseT4
- Appears in Collection
- EE-Theses_Master(석사논문)
- Files in This Item
- There are no files associated with this item.
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