DEVS 형식론에 의한 하드웨어 모델링 및 합성가능한 VHDL Code의 자동 생성 = Hardware modeling based on DEVS formalism and automatic generation of synthesizable VHDL code
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.advisor | 박규호 | - |
| dc.contributor.advisor | Park, Kyu-Ho | - |
| dc.contributor.author | 이영무 | - |
| dc.contributor.author | Lee, Young-Moo | - |
| dc.date.accessioned | 2011-12-14T01:39:21Z | - |
| dc.date.available | 2011-12-14T01:39:21Z | - |
| dc.date.issued | 1996 | - |
| dc.identifier.uri | http://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=108801&flag=dissertation | - |
| dc.identifier.uri | http://hdl.handle.net/10203/36880 | - |
| dc.description | 학위논문(석사) - 한국과학기술원 : 전기및전자공학과, 1996.8, [ vii, 91 p. ] | - |
| dc.language | kor | - |
| dc.publisher | 한국과학기술원 | - |
| dc.subject | 합성가능한 VHDL | - |
| dc.subject | HDEVS 형식론 | - |
| dc.subject | 하드웨어 모델링 | - |
| dc.subject | DEVS 형식론 | - |
| dc.subject | VHDL Code 자동 생성 | - |
| dc.subject | VHDL code Generation | - |
| dc.subject | Synthesizable VHDL | - |
| dc.subject | HDEVS formalism | - |
| dc.subject | Hardware modeling | - |
| dc.subject | DEVS formalism | - |
| dc.title | DEVS 형식론에 의한 하드웨어 모델링 및 합성가능한 VHDL Code의 자동 생성 = Hardware modeling based on DEVS formalism and automatic generation of synthesizable VHDL code | - |
| dc.type | Thesis(Master) | - |
| dc.identifier.CNRN | 108801/325007 | - |
| dc.description.department | 한국과학기술원 : 전기및전자공학과, | - |
| dc.identifier.uid | 000953445 | - |
| dc.contributor.localauthor | 박규호 | - |
| dc.contributor.localauthor | Park, Kyu-Ho | - |
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