DEVS 형식론에 의한 하드웨어 모델링 및 합성가능한 VHDL Code의 자동 생성 = Hardware modeling based on DEVS formalism and automatic generation of synthesizable VHDL code

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dc.contributor.advisor박규호-
dc.contributor.advisorPark, Kyu-Ho-
dc.contributor.author이영무-
dc.contributor.authorLee, Young-Moo-
dc.date.accessioned2011-12-14T01:39:21Z-
dc.date.available2011-12-14T01:39:21Z-
dc.date.issued1996-
dc.identifier.urihttp://library.kaist.ac.kr/search/detail/view.do?bibCtrlNo=108801&flag=dissertation-
dc.identifier.urihttp://hdl.handle.net/10203/36880-
dc.description학위논문(석사) - 한국과학기술원 : 전기및전자공학과, 1996.8, [ vii, 91 p. ]-
dc.languagekor-
dc.publisher한국과학기술원-
dc.subject합성가능한 VHDL-
dc.subjectHDEVS 형식론-
dc.subject하드웨어 모델링-
dc.subjectDEVS 형식론-
dc.subjectVHDL Code 자동 생성-
dc.subjectVHDL code Generation-
dc.subjectSynthesizable VHDL-
dc.subjectHDEVS formalism-
dc.subjectHardware modeling-
dc.subjectDEVS formalism-
dc.titleDEVS 형식론에 의한 하드웨어 모델링 및 합성가능한 VHDL Code의 자동 생성 = Hardware modeling based on DEVS formalism and automatic generation of synthesizable VHDL code-
dc.typeThesis(Master)-
dc.identifier.CNRN108801/325007-
dc.description.department한국과학기술원 : 전기및전자공학과, -
dc.identifier.uid000953445-
dc.contributor.localauthor박규호-
dc.contributor.localauthorPark, Kyu-Ho-
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EE-Theses_Master(석사논문)
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